(a) Field of the Invention
The present invention relates to an image processing system and, more particularly, to an image processing system suitable for decoding compressed coded data of still pictures in, for example, digital television tuners, video telephone sets, and personal computers.
(b) Description of the Related Art
Some conventional image processing systems utilize a two-dimensional prediction scheme for prediction coding of still pictures. In this scheme, the value of one pixel on a scanning line is predicted on the basis of the value of the several pixels immediately preceding the one pixel. In this process, a predicted error signal (or differential value) is quantized, and instead of the quantized value of the predicted error itself, a quantized number corresponding to the quantized value of the predicted error is transmitted after being subjected to variable-length coding. A scheme wherein a prediction coefficient used in the prediction is set to xe2x80x9c1xe2x80x9d is called two-dimensional DPCM (Differential Pulse Code Modulation).
In the two-dimensional DPCM scheme, when still picture data obtained by raster scanning is stored in a frame buffer in the format of compressed still picture data, the pixel data for the first pixel on each line is stored in the frame buffer as an uncoded true value. In contrast, the pixel data for each pixel subsequent to the first pixel on each scanning line is stored in the frame buffer as a coded differential data obtained by coding a difference between the true value of the pixel and that of the preceding pixel. This compression processing decreases the number of memory cells used for storing data per a unit image size.
When picture data compressed by the two-dimensional DPCM scheme are to be decoded, the true value of the first pixel on each scanning line is first read out from the frame buffer. The decoder circuit outputs the true value data as the pixel data for the subsequent pixels on the each scanning line based on the true value data for the preceding pixel and the pixel data in terms of coded differential data by calculating a sum of the true value for the preceding pixel and decoded differential data.
In the conventional image processing system, when compressed still picture data for a specified small area in a screen of a display unit are to be decoded and output for display in the display unit, data for the other area falling outside the small area are also read out from the frame buffer and decoded pixel by pixel from the first pixel on each scanning line that is located before the small area to the last pixel on the each scanning line. Therefore, if the number of pixels falling outside the small area is large, the timing of start for data processing must be sufficiently earlier than the timing of start for the display of data for the small area, necessitating a complicated sequence.
Further, in the decoding processing, simultaneously with the operation of temporarily storing decoded pixel data of the small area into a decoded data buffer, an enlargement/reduction processing is generally performed by use of a dedicated enlargement/reduction circuit provided separately from the decoding circuit. The provision of decoding circuit and the enlargement/reduction circuit as respective dedicated circuits result in an increase in the circuit scale. In this case, a data buffer having a large storage capacity is required in order to increase the speed of the decoding processing.
In view of the foregoing, an object of the present invention is to provide an image processing system which performs high-speed decoding of pixel data falling outside of an arbitrary small area in a screen, thereby increasing the overall speed of decoding processing and an enlargement/reduction processing in the small area.
Another object of the present invention is to provide an image processing system which is capable of obviating necessity for providing a dedicated buffer for the enlargement/reduction processing.
The present invention provides an image processing system for decoding a compressed picture data, comprising:
a decoding block including a plurality of decoding sections each calculating a first true value data for one pixel based on a coded differential data for the one pixel and a second true value data for another pixel preceding the one pixel, the plurality of decoding sections being coupled together in a cyclic order such that the second true value data being calculated by another of the decoding sections; and
an address control block for detecting whether the one pixel has an address equal to an address of a start point of a specified area, to generate a display start point signal, the plurality of decoding sections calculating the first true value data for the respective one pixels at a time in a single clock cycle before generation of the display start point signal on a scanning line.
In accordance with the image processing system of the present invention, compressed picture data can be decoded for the pixels outside the specified area at a higher speed corresponding to the number of the decoding sections. Further, the number of operational decoding sections may be changed in accordance with an enlargement/reduction ratio of the image size, which obviates the necessity of provision of a dedicated buffer.
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.